Filling Micro-Vias Theoretical and Practical Aspects - Sponsored Whitepaper

Via filling becomes a necessity when chip carriers and other components shall be directly mounted onto the vias and when via dimensions are as small as the Cu layer to be deposited. During the process of blind and through microvia filling one observes a throwing power change with the deposition time and depending on the via dimensions, respectively. A change of the current density profile can be beneficial to meet via filling requirements in production. The filling capability depends on many chemical and physical parameters. In the paper presented the influence of the major variables, ranging from organic and inorganic additives to pulse parameters are being explained. Examples from horizontal and vertical production lines are shown and optimum via geometry considerations will be discussed.

Introduction With increasing number of interconnects new technologies in PCB and package manufacturing, like the sequential built up (SBU), are being developed. At the same time structures and distances on the panels are being sized down to degree that a filling of the so-called microvias becomes a necessity. Thereby efficient fan-out by mounting components and packages directly on the vias is assured. Vias with dimensions in the range of the Cu thickness to be deposited can only be plated with sufficient process security, if filled without inclusions. Certain IC package applications have this requirement for blind and through vias.

Some theoretical considerations When looking at the plating process for microvias (MVs), one can conceive the most characteristic and most application relevant feature of these small structures. What has been a constant and measurable entity in printed circuit board plating so far, becomes – when treating microvias – a variable and therefore a great unknown.